Efficient Queuing Architecture for a Buffered Crossbar Switch

This paper presents a modified architecture for a buffered crossbar switch that overcomes the memory bottleneck with only a minor impact on performance. The proposed architecture uses two levels of backpressure with different constraints on round trip time. Buffered crossbars are considered an alternative to bufferless crossbars mainly because the latter requires a complex scheduling algorithm that matches input with output. Buffered crossbars require only a simple scheduler that operates independently for each output queue column. The memory amount required for a buffered crossbar is proportional to the square of the number of ports and the round trip time. The proposed architecture reduces the amount of memory in the buffered crossbar without increasing the scheduling complexity. Key-Words: Buffered Crossbar, Packet switching, SpeedUp